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Chapter 3: Specifications
Functional Description
When the receiver detects a disparity error, the rderr signal is asserted.
Figure 3–7 shows a block diagram of the decoder.
Figure 3–7. Decoder
3–7
clk
reset_n
idle_del
ena
datain [9:0]
rdin
rdforce
v alid
datao u t [7:0]
ko u t
kerr
rderr
rdo u t
rdcascade
Cascaded Decoding
Two decoders can be cascaded to decode two words simultaneously. The decoders are
cascaded—in a similar fashion as the encoders—by connecting the rdcascade output
of the first decoder to the rdin input of the second decoder, and by connecting the
rdout output of the second decoder to the rdin input of the first decoder. The rdforce
inputs of both decoders must be tied high.
To enable cascaded decoding, the data paths fed by the rdin and rdforce inputs are
not pipelined. If these inputs are to be used in non-cascaded decoders, they should be
delayed by one clock cycle with respect to their corresponding datain and kin inputs.
Decoding Latency
The decoder is pipelined, thus it takes two clock cycles for a character to be decoded.
The decoded value—corresponding to the value of datain sampled by the decoder on
rising edge n —is output shortly after rising edge n+1 , and is available to be sampled
on the rising edge of clock cycle n+2 . (See Figure 3–6 on page 3–6 ).
Figure 3–8. Decoder Timing Diagram
clk
n
n+1 n+2 n+3
datain, ena
datao u t, ko u t
kerr, rdo u t, rderr
rdforce, rdin
a
b
a
c
a
b
d
b
c
e
c
d
f
d
e
g
e
f
May 2011
Altera Corporation
8B10B Encoder/Decoder MegaCore Function User Guide
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